module con_signal (
input mova, movb, movc, movd, add, sub, jmp, jg, g, in1, out1, movi, halt, sm,
input [7:0] ir,
//control au to perform different operation
output reg[3:0] au_ac,
//s:ram's address source;reg_sr:source;reg_dr:destinstion
output reg[1:0] s, reg_sr, reg_dr,
//pc_ld:1 R3->pc;pc_in:pc++;reg_we:write inout->reg;ram_re/we:ram read/write;
//ir_ld:take instruction;mux_s:reg data source
output reg pc_ld, pc_in, reg_we, ram_re, ram_wr, au_en, mux_s, ir_ld, gf_en, sm_en, in_en, out_en) ;
always @(*) begin
//sm transover control
sm_en=~halt;
//register instruction:sm=0 read;sm=1 carry out;
ir_ld=~sm;
//ram
ram_re=(~sm)| movc | movi ;
ram_wr=movb;
mux_s=mova | movb | movc | movi | add | sub | in1;
//au
au_ac[3:0]=ir[7:4];
au_en=add | sub | mova | movb | out1;
gf_en=sub ;
//pc
pc_ld=jmp| (jg&g) ;
pc_in=(~sm) | movi ;
//in&out
in_en=in1;
out_en=out1;
//reg 
reg_sr[1:0]=ir[1:0];
reg_dr[1:0]=ir[3:2];
reg_we= mova | movc |movd | movi | add | sub | in1;
//3-1 select
if(sm == 1 && ( mova == 1 || movc==1)) s=2'b01;
else if(sm == 1&& movb == 1) s=2'b10;
else if( sm==0 )s=2'b00;
else s=2'b00;
end
endmodule